1. Field of the Invention
The present invention relates to an optical receiver circuit used in an optical communication system. More particularly, the invention pertains to an optical receiver circuit suitable for receiving burst digital data, and an optical module using the same in an optical communication system.
2. Description of the Related Art
In general, unlike timewise continuous signal output from video and audio equipment, digital data output from computers typical of information processing equipment has a bursty characteristic, i.e., data is output intensively for a certain period of time and no data is output for the remaining period of time. In an optical communication system for transmitting and receiving such burst data, it is required to provide an optical receiver circuit capable of receiving burst data with high stability.
Referring to FIG. 1, there is shown an example of a conventional optical receiver circuit 100 disclosed in Japanese Unexamined Patent Publication. No. 8 (1996)-84160. FIGS. 2A to 2E show waveforms in respective parts of the optical receiver circuit 100.
Upon receiving an optical signal, a photodetector 1 converts the received optical signal into an electrical signal, which is then supplied to a pre-amplifier 2. The pre-amplifier 2 amplifies the electrical signal supplied from the photodetector 1 to produce positive and negative signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d.
Under condition that an offset voltage Voff exists in an output of the pre-amplifier 2, signal levels of the positive and negative signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d in a no-input signal state are xe2x80x9cVoffxe2x80x9d and xe2x80x9cxe2x88x92Voffxe2x80x9d respectively, xe2x80x9c0xe2x80x9d levels thereof in a burst data receiving state are also xe2x80x9cVoffxe2x80x9d and xe2x80x9cxe2x88x92Voffxe2x80x9d respectively, and xe2x80x9c1xe2x80x9d levels thereof in the burst data receiving state are xe2x80x9cV+Voffxe2x80x9d and xe2x80x9cxe2x88x92Vxe2x88x92Voffxe2x80x9d respectively (FIG. 2A).
A first peak hold circuit 3 detects a value of a maximum level of the positive signal xe2x80x9caxe2x80x9d (hereinafter referred to as a peak value) and generates an output signal xe2x80x9ccxe2x80x9d, which has a signal level of offset voltage xe2x80x9cVoffxe2x80x9d in the no-input signal state and a xe2x80x9c1xe2x80x9d level voltage xe2x80x9cV+Voffxe2x80x9d in the data receiving state.
A second peak hold circuit 4 detects a peak value of the negative signal xe2x80x9cbxe2x80x9d, and generates an output signal xe2x80x9cdxe2x80x9d, which has a signal level of offset voltage xe2x80x9cxe2x88x92Voffxe2x80x9d in the no-input signal state and a xe2x80x9c0xe2x80x9d level voltage xe2x80x9cxe2x88x92Voffxe2x80x9d in the data receiving state (FIG. 2C).
In FIG. 1, resistors 61 to 64 and a differential amplifier 65 constitute an offset canceller 6. When the output signal xe2x80x9ccxe2x80x9d of the first peak hold circuit 3 and the negative signal xe2x80x9cbxe2x80x9d are supplied to a negative input terminal of the differential amplifier 65 through the resistors 61 and 63 having the same resistance value, the levels of the signals xe2x80x9cbxe2x80x9d and xe2x80x9ccxe2x80x9d are averaged to provide a signal xe2x80x9cfxe2x80x9d as a negative input to the differential amplifier 65. In the signal xe2x80x9cfxe2x80x9d thus provided, a xe2x80x9c0xe2x80x9d level voltage in the data receiving state is xe2x80x9cV/2xe2x80x9d, and a xe2x80x9c1xe2x80x9d level voltage in the data receiving state and an output voltage in the no-input signal state are zero (FIG. 2B).
In the same manner as mentioned above, when the positive signal xe2x80x9caxe2x80x9d and the output signal xe2x80x9cdxe2x80x9d of the second peak hold circuit 4 are supplied to a positive input terminal of the differential amplifier 65 through the resistors 62 and 64 having the same resistance value, the levels of the signals xe2x80x9caxe2x80x9d and xe2x80x9cdxe2x80x9d are averaged to provide a signal xe2x80x9cexe2x80x9d as a positive input to the differential amplifier 65. In the signal xe2x80x9cexe2x80x9d thus provided, a xe2x80x9c0xe2x80x9d level voltage in the data receiving state and an output voltage in the no-input signal state are zero, and a xe2x80x9c1xe2x80x9d level voltage in the data receiving state is xe2x80x9cV/2xe2x80x9d.
Through the above signal processing, offset voltages xe2x80x9cVoffxe2x80x9d contained in the signals xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d output from the pre-amplifier 2 can be canceled mutually. That is, the signals xe2x80x9cexe2x80x9d and xe2x80x9cfxe2x80x9d input to the differential amplifier 65 are subjected to differential amplification on a basis of gain G, thereby outputting a positive signal xe2x80x9cgxe2x80x9d and a negative signal xe2x80x9chxe2x80x9d (FIG. 2D). These output signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d are not affected by output offset xe2x80x9cVoffxe2x80x9d of the pre-amplifier 2, and both the xe2x80x9c1xe2x80x9d level pulse duty ratio (half value width of pulse per cycle) and the xe2x80x9c0xe2x80x9d level pulse duty ratio in the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d are 0.5, i.e. , the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d are equivalent to each other.
The signal xe2x80x9cgxe2x80x9d output from the differential amplifier 65 is distinguished as a binary signal in the comparator 7 by comparing with the signal xe2x80x9chxe2x80x9d, thereby providing a positive output signal xe2x80x9cixe2x80x9d. In the comparator 7, a binary judgment is carried out to check whether a difference voltage between the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d is in a positive state or a negative state. In this case, since both the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d vary symmetrically, the comparator 7 performs the binary judgment with a judgment reference voltage (threshold) which is equivalent to an average value of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels of the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d. If the judgment reference voltage in the comparator 7 can be substantially set to an average value of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels of the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d, a binary signal xe2x80x9cixe2x80x9d having an equal duty ratio may be attained as an output of the comparator 7 regardless of a value of output voltage xe2x80x9cVxe2x80x9d from the pre-amplifier 2 in the data receiving state.
However, in the circuit configuration shown in FIG. 1, the levels of the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d are equal to each other in the no-input signal state. Consequently, an operation of comparing the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d in the no-input signal state becomes unstable, making it difficult to attain a correct result in distinction by the comparator 7. When the pre-amplifier 2 is in the no-input signal state and when the pre-amplifier 2 outputs a xe2x80x9c0xe2x80x9d level signal of data input, it is required for the comparator 7 to distinguish the input signal xe2x80x9cgxe2x80x9d as a low level. Hence, for attaining a correct result of binary judgment in the no-input signal state, it is inevitable to use a substantial judgment reference voltage having a value larger than the average value of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels of the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d.
If the judgment reference voltage is larger than the average value of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels of the signals xe2x80x9cgxe2x80x9d and xe2x80x9chxe2x80x9d, however, there arises a problem of deterioration in duty ratio of the output signal xe2x80x9cixe2x80x9d. FIG. 2E shows a waveform of the output signal xe2x80x9cixe2x80x9d having a deteriorated duty ratio. The duty ratio of the output signal xe2x80x9cixe2x80x9d varies depending on an amplitude voltage xe2x80x9cVxe2x80x9d of the positive signal xe2x80x9caxe2x80x9d, i.e., a magnitude of the signal output from the photodetector 1.
It is therefore an object of the present invention to obviate the above-mentioned disadvantage of the related art by providing an optical receiver circuit having a duty ratio which does not deteriorate in a burst data receiving state and an optical module containing the optical receiver circuit.
In accomplishing this object of the present invention and according one aspect thereof, there is provided an optical receiver circuit in which a level shift circuit is disposed between a first peak hold circuit for detecting a maximum level of a positive signal and an offset canceller circuit so that an output signal level of the first peak hold circuit is made higher than an actual level for a period of time that an amplitude of a positive signal output from a pre-amplifier is smaller than a predetermined amplitude value.
More specifically, according to the present invention, there is provided a optical receiver circuit comprising: a pre-amplifier for amplifying a signal supplied from a photodetector to output positive and negative signals; a first peak hold circuit for detecting a maximum level of the positive signal output from the pre-amplifier; a second peak hold circuit for detecting a maximum level of the negative signal output from the pre-amplifier; an offset canceller circuit for compensating the positive signal at an output signal level of the second peak hold circuit, for compensating the negative signal at an output signal level of the first peak hold circuit, and for then performing differential amplification; and a level shift circuit for replacing the output signal level of the first peak hold circuit with a predetermined signal level higher than an actually detected maximum signal level for a period of time that light input to the photodetector is in a no-input signal state; whereby the negative signal is compensated at the predetermined signal level.
In the circuit arrangement mentioned above, a level of a positive signal input to a comparator in the no-input signal state can be lowered to allow the use of an average value of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels as a judgment reference voltage. Therefore, according to the present invention, a signal level in the no-input signal state can be reliably distinguished as a low level, making it possible to implement an optical receiver circuit capable of preventing deterioration in duty ratio.
The level shift circuit noted above, for example, comprises a bottom hold circuit for holding a minimum level value of the positive signal output from the pre-amplifier, a bottom level shift circuit for increasing an output signal level of the bottom hold circuit by a predetermined value, and a maximum level selector circuit for selectively delivering an output signal of the first peak hold circuit or an output signal of the bottom level shift circuit, whichever is higher in terms of signal level.